Integrated circuits (ICs) may be subject to manufacturing defects that may result in current leakage (e.g., leakage from a signal pin to the power supply (VCC), to ground (VSS) or to a neighboring signal pin or pins). It is desirable to perform testing to detect such leakage defects to avoid shipping defective devices to customers.
With increasing input/output (I/O) speeds, differential signaling (e.g., so-called low voltage differential signals—LVDS) is increasingly used. Interfaces for differential signaling may employ capacitive coupling to block DC currents and voltages at the receiver differential amplifier. The required capacitors may be on-die or off-die, but in either case may prevent conventional DC leakage tests at nodes beyond the capacitors. Also, conventional low speed test equipment may not be suitable for implementation of standard leakage testing for high speed I/O devices.